manuais SMSC LAN9312

Smsc LAN9312 Manual do Utilizador (458 páginas)

Marca: Smsc | Categoria: Acessórios para Computador | Tamanho: 4.49 MB |

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Índice

High Performance

1

Two Port 10/100 Managed

1

Ethernet Switch with 32-Bit

1

Non-PCI CPU Interface

1

Table of Contents

3

DATASHEET

10

List of Figures

12

List of Tables

14

Chapter 1 Preface

16

1.2 Buffer Types

18

1.3 Register Nomenclature

19

Chapter 2 Introduction

20

2.2 Block Diagram

21

2.2.3 Switch Fabric

23

2.2.4 Ethernet PHYs

23

2.2.6 Host MAC

24

2.2.8 1588 Time Stamp

24

2.3 System Configuration

25

3.1 Pin Diagrams

26

128-XVTQFP

27

3.2 Pin Descriptions

28

EEPROM_SIZE_1

31

EEPROM_SIZE_0

32

PHY_ADDR_SEL

32

4.1 Clocks

36

4.2 Resets

36

4.2.1 Chip-Level Resets

37

4.2.2 Multi-Module Resets

38

4.2.3 Single-Module Resets

39

4.2.4 Configuration Straps

40

4.3 Power Management

46

Chapter 5 System Interrupts

49

5.2.3 Ethernet PHY Interrupts

52

5.2.4 GPIO Interrupts

52

5.2.5 Host MAC Interrupts

52

5.2.8 Software Interrupt

54

5.2.9 Device Ready Interrupt

54

Chapter 6 Switch Fabric

55

6.2.2 Switch Fabric CSR Reads

57

6.3 10/100 Ethernet MACs

60

6.3.2 Transmit MAC

62

6.4 Switch Engine (SWE)

63

6.4.2 Forwarding Rules

66

6.4.4 VLAN Support

70

6.4.5 Spanning Tree Support

70

6.4.7 Broadcast Storm Control

74

6.4.9 Port Mirroring

75

6.4.11 Counters

76

6.5 Buffer Manager (BM)

77

6.5.7 Counters

81

Chapter 7 Ethernet PHYs

82

7.2 Port 1 & 2 PHYs

83

7.2.1 100BASE-TX Transmit

84

7.2.2 100BASE-TX Receive

87

7.2.3 10BASE-T Transmit

89

7.2.4 10BASE-T Receive

89

7.2.5 PHY Auto-negotiation

90

7.2.6 HP Auto-MDIX

93

7.2.7 MII MAC Interface

93

7.2.8 PHY Management Control

94

7.2.9 PHY Power-Down Modes

94

7.2.10 PHY Resets

95

7.3 Virtual PHY

96

7.3.2 Virtual PHY Resets

98

8.1 Functional Overview

99

8.2 Host Memory Mapping

99

8.3 Host Endianess

99

8.4 Host Interface Timing

101

8.4.4 PIO Reads

106

8.4.5 PIO Burst Reads

107

8.4.8 PIO Writes

110

8.5 HBI Interrupts

111

9.1 Functional Overview

112

9.2 Flow Control

113

9.4 Address Filtering

114

9.4.1 Perfect Filtering

115

9.4.2 Hash Only Filtering

115

9.4.3 Hash Perfect Filtering

115

9.5 Wake-up Frame Detection

116

9.5.1 Magic Packet Detection

118

9.6 Host MAC Address

119

9.7 FIFOs

120

9.8 TX Data Path Operation

122

9.8.1 TX Buffer Format

124

9.8.2 TX Command Format

124

9.8.3 TX Data Format

126

9.8.4 TX Status Format

127

9.8.6 Transmit Examples

128

9.8.7 Transmitter Errors

131

9.9 RX Data Path Operation

132

9.9.2 RX Packet Format

134

9.9.3 RX Status Format

135

9.9.5 Receiver Errors

136

10.1 Functional Overview

137

10.2 I

137

10.2.2 I

139

C EEPROM

139

10.2.3 Microwire EEPROM

144

10.2.4 EEPROM Loader

149

11.1 Functional Overview

154

11.1.2 Block Diagram

155

11.2 IEEE 1588 Time Stamp

156

11.2.1 Capture Locking

157

11.2.2 PTP Message Detection

158

11.3 IEEE 1588 Clock

159

11.4 IEEE 1588 Clock/Events

160

11.5 IEEE 1588 GPIOs

160

11.6 IEEE 1588 Interrupts

160

12.1 General Purpose Timer

161

12.2 Free-Running Clock

161

13.1 Functional Overview

162

13.2 GPIO Operation

162

13.2.2 GPIO Interrupts

163

13.3 LED Operation

164

14.1 TX/RX FIFO Ports

167

14.2.1 Interrupts

172

14.2.2 Host MAC & FIFO’s

180

14.2.3 GPIO/LED

192

14.2.4 EEPROM

197

14.2.5 IEEE 1588

201

14.2.6 Switch Fabric

229

14.2.8 Virtual PHY

245

14.2.9 Miscellaneous

259

Offset: 5h Size: 32 bits

276

14.4.1 Virtual PHY Registers

285

0 0 Manual mode, no crossover

303

0 1 Manual mode, crossover

303

1 0 Auto-MDIX mode

303

14.5.1 General Switch CSRs

318

14.5.3 Switch Engine CSRs

366

14.5.4 Buffer Manager CSRs

411

15.2 Operating Conditions**

440

15.3 Power Consumption

441

15.4 DC Specifications

442

15.5 AC Specifications

443

15.5.4 PIO Read Cycle Timing

446

15.5.8 PIO Write Cycle Timing

450

15.5.10 Microwire Timing

452

15.6 Clock Circuit

453

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