SMSC LAN91C111 Manual do Utilizador Página 69
- Página / 128
- Índice
- MARCADORES
- LAN91C111 1
- 10/100 Non-PCI 1
- Ethernet Single Chip 1
- MAC + PHY 1
- Table of Contents 3
- List of Figures 6
- List of Tables 7
- Chapter 1 General Description 8
- Chapter 2 Pin Configurations 9
- 128 PIN QFP 10
- Chapter 3 Block Diagrams 11
- Protocol 12
- Ethernet 12
- Datasheet 13
- Chapter 4 Signal Descriptions 14
- 6.1 Buffer Types 19
- 7.1 Clock Generator Block 20
- 7.2 CSMA/CD Block 20
- 7.3 MMU Block 20
- 7.4 BIU Block 21
- 7.5 MAC-PHY Interface 21
- 7.5.2 Management Data Timing 22
- 7.6 Serial EEPROM Interface 25
- 7.7 Internal Physical Layer 25
- 7.7.1 MII Disable 27
- 7.7.2 Encoder 27
- 7.7.3 Decoder 27
- 7.7.4 Clock and Data Recovery 29
- 7.7.5 Scrambler 29
- 7.7.6 Descrambler 29
- 7.7.8 Twisted Pair Receiver 33
- 7.7.9 Collision 35
- 7.7.10 Start of Packet 35
- 7.7.11 End of Packet 36
- 7.7.13 Jabber 40
- 7.7.15 Full Duplex Mode 41
- 7.7.16 Loopback 41
- 7.7.17 PHY Powerdown 41
- 7.7.18 PHY Interrupt 41
- 7.8 Reset 42
- CRC (4 BYTES) 43
- 8.2 Receive Frame Status 44
- 8.3 I/O Space 45
- 8.4 Bank Select Register 46
- 8.8 Bank 0 - Counter Register 50
- 8.20 Bank 2 - Data Register 62
- 8.25 Bank 3 - RCV Register 68
- Chapter 9 PHY MII Registers 70
- Management 84
- DATASHEET 101
- Chapter 14 Timing Diagrams 110
- Chapter 15 Package Outlines 126
- Chapter 16 Revision History 128
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